Analog-to-digital converters are widely used in many electronic devices, and are key components in interfaces between the analog world and the digital domain. In order to satisfy increasingly demanding application requirements, the performance of such converters, for example in terms of resolution, speed and power consumption, are increasing. High-resolution, high-speed and low power converters, for example greater than 12-bit resolution at >20M samples per second and <400 mW power consumption, cannot rely on the matching performances of standard fabrication processes. Various calibration techniques tend therefore to be used.
FIG. 1 represents an exemplary known pipeline stage 100 incorporating element calibration, as described in U.S. Pat. No. 5,499,027. The DAC element under calibration 110 is connected to reference voltage +/−Vref according to a calibration state signal. FIG. 2 shows the two calibration states S1, S2 on the transfer curve 210 of the stage 100, the difference between the two states being given by Δ=S1−S2. Extraction of the element error is carried out by averaging the difference between the states, i.e. εelement=(Δ−Δideal)/Δideal with Δideal=+Vref. One can see that the processing is applied with zero input, i.e. Vin is held at 0V while calibration of the element 110 takes place.
The above technique is well suited for multi-bit pipeline converters using m-bit stages (with m being an integer). Such a converter uses 2m−1 DAC elements. The number of switches in the DAC 120, however, limit the maximum achievable working frequency of the whole converter 100. In order to increase the working frequency, a (m−0.5)-bit, or half integer bit, stage may be used because only 2m−1−1 capacitors and a corresponding number of switches are needed, thus limiting drastically the number of inter-connections. In an (m−0.5)-bit stage, however, the element calibration described above is not usable because the calibration states are equal to the coding capabilities of the following stages, as shown in FIG. 3. In practice, the calibration algorithm is therefore no longer viable.
As described herein, for a given pipeline stage the coding capability at the output of the stage relates to the range a signal can be further coded by subsequent pipeline stages. Exceeding this coding capability results in the introduction of non-linear behaviour, leading to incorrect calibration. For example, for a coding capability of between 1 and 10, numbers greater than 10 are coded as 10 numbers lower than 1 are coded as 1.